The I2C-bus (inter-integrated circuit) is a de facto world standard that is now implemented in thousands of different ICs manufactured by scores of different companies. Additionally, the versatile I2C-bus is used in various control architectures such as System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA).
In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes: some intelligent control, usually a single-chip microcontroller; general-purpose circuits like LCD and LED drivers, remote I/O ports, RAM, EEPROM, real-time clocks or A/D and D/A converters; and application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, temperature sensors, and smart cards.
To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the “Inter IC,” I2C, or I2C bus. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves many interfacing problems encountered when designing digital control circuits.
Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL). Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers. Collision detection and arbitration is supported to prevent data corruption if two or more masters simultaneously initiate data transfer.
Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, up to 3.4 Mbit/s in the High-speed mode, or up to 5 Mbit/s in Ultra Fast-mode. On-chip filtering rejects spikes on the bus data line to preserve data integrity. The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance.
The I2C protocol and operation is described in more detail in available documents; see, e.g. “UM10204 I2C-bus specification and user manual”, Rev. 5; 9 Oct. 2012, NXP Semiconductors.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.